- The SOT-MRAM achieves 0,35 ns and 156 fJ without auxiliary field, maintaining E/kBT≈70 and TMR≈170%.
- Tungsten, due to its high spin torque efficiency, reduces write energy and accelerates switching.
- STT-MRAM is already commercially available in aerospace environments with high resistance, -40 to 125 ºC and 45 ns access.
- The combination of SOT, heavy materials, and multiferroic pathways brings MRAM closer to replacing SRAM at certain levels.
SOT-MRAM memory with tungsten layer has crept into the high-level debate about the future of computing for one clear reason: it promises to unite breakneck speed, non-volatility, and ultra-low power consumption on the same chip. In the era of AI and IoT, where every milliwatt counts, this magnetoresistive technology aims to redefine both the High-performance RAM such as non-volatile storage.
Beyond the headline, what is really changing the game These are concrete advances: cells that write in 0,35 nanoseconds without an auxiliary field, write powers of just 156 fJ and improvements of 35% compared to previous generations of SOT. All this while maintaining thermal stability and a Very high TMR, key ingredients for bringing MRAM from the lab to the 300mm factory and then to the laptop, mobile phone, or data center.
What is SOT-MRAM and why is everyone talking about it?
SOT-MRAM (Spin-Orbit Torque MRAM) is a variant of MRAM that uses spin-orbit torques generated in heavy metal layers to switch the magnetic state of a "free layer" within a magnetic tunnel junction (MTJ). Unlike DRAM and SRAM, it doesn't require refreshing; and compared to flash, it writes quickly, without high voltages, and with virtually unlimited endurance.
In a typical MTJ coexist a fixed ferromagnetic layer (reference), an ultrathin insulating barrier, and a free ferromagnetic layer whose orientation can be changed. If both layers are aligned, the resistance is lower; if they are antiparallel, the resistance increases. This difference is measured during reading to encode 0/1, nondestructively and very quickly.
SOT-MRAM places the write current in a plane parallel to the cell, using the spin Hall effect in materials such as tungsten, tantalum, or platinum to inject angular momentum into the free layer. The advantage? Extremely high speeds and less wear, in addition to physically separating the read and write paths, which improves the reliability of the entire system.
Physics in two strokes: spin, MTJ and the two switching paths (STT vs SOT)
The electron spin can be thought of as a tiny quantum compass that points “up” or “down.” Tunnel magnetoresistance This occurs because electrons pass through the insulating barrier with varying probabilities depending on the relative alignment of the two ferromagnetic layers. This variation in resistance is the basis for reading MRAM cells.
In STT-MRAM (Spin Transfer Torque), current flows through the MTJ and transfers spin torque to reorient the free layer. It is the most commercially mature option, widely used in microcontrollers and embedded systems. In SOT-MRAM, current flows through an adjacent metal layer; the spin-Hall effect generates a spin current that switches the free layer. SOT is generally faster and less intrusive in MTJ, with a bright future as a candidate to replace SRAM in caches.
Complementary solutions such as devices have also been explored. multiferroics where electric fields help to fix or reverse magnetizations, and “canted” designs that facilitate writing without the need for an external auxiliary field, simplifying the circuit and improving efficiency.
Tohoku jump: 0,35 ns, 156 fJ and writing without auxiliary field
A team from Tohoku University has demonstrated a tilted SOT-MRAM capable of writing in 0,35 nanoseconds without using an external magnetic field. The key lies in a "canted" design with a 75° angle and its optimization through micromagnetic simulation and a 300 mm wafer process, suitable for scaling up to industrial manufacturing.
Angle and angle optimization anisotropy of the free layer This has allowed write power to be reduced to 156 femtojoules, 35% less than comparable previous SOT technologies, while maintaining an E/kBT thermal stability factor of 70 (stability against thermal fluctuations) and a very high TMR ratio (170%). In other words: top speed, minimal consumption, and robustness.
These parameters clear three major barriers: performance, efficiency and compatibility with a manufacturing flow of 300 mm. This opens the door to its use in data centers, development of AI, IoT, smartphones and demanding embedded systems, where the combination of non-volatility and low energy is pure gold.
All of this aligns with a goal that the team itself expressed: to adapt MRAM to a society accelerated by AI and the Internet of Things, prioritizing reduce writing energy without sacrificing the ultra-fast speeds demanded by today's hardware.
What does the tungsten layer contribute to SOT-MRAM?
In SOT devices, the heavy metal layer that generates the spin-orbit torque is crucial. Tungsten (especially in its β phase) It stands out for its high spin Hall angle, which translates into greater efficiency in converting charge current into spin current. In plain English: less energy to change the bit and faster switching times.
Along with tungsten, metals such as tantalum or PlatinumIn fact, academic research has shown improvements by incorporating nanometer-sized layers of platinum beneath magnetic layers, facilitating switching and reducing power consumption during write operations. In all cases, the idea is the same: materials with strong spin-orbit coupling that efficiently inject spin into the free layer.
The choice of heavy metal impacts critical parameters: writing stream (and therefore power), high-speed reliability, compatibility with MTJ stacking and the BEOL of the CMOS process. Tungsten shines for its SOT efficiency, but the industry also values its integration into advanced processes, which is key when considering cutting-edge nodes.
It is worth noting that Tohoku's advances in tilted cells focus on architecture and anisotropy engineering, while other lines, such as those based on platinum foil or multiferroic approaches, are exploring complementary paths. Everything contributes to a common goal: less energy per bit, more speed, and processes compatible with mass production.
MRAM and STT-MRAM Today: Real-World Products, Radiation, and Extreme Environments
As SOT-MRAM fine-tunes its large-scale jump, the STT-MRAM is now on the marketThere are 64 Mb and 1 Gb devices targeted at aerospace and space applications with hermetic ceramic packages (CLGA/CBGA) and RAD-HARD, RAD-Tolerant, and non-hardened variants. These memories offer truly random read and write access, high resistance to magnetic flux (reduced shielding requirements), and an excellent power profile.
In harsh environments, these components guarantee data retention of more than 10 years between -40 and +125°C, with typical voltages of 2,7 to 3,6 V and minimum access times of around 45 ns in the military range. This means they are not only unaffected by radiation, but also perform reliably under demanding thermal conditions.
Recent developments have multiplied densities: a jump from 16 Mb to 64 Mb in the same format, and up to 1 Gb (32M x 32) with 22 nm pMTJ STT-MRAM technology. There is talk of improvements in bit density on the order of several thousand Mb/mm² compared to previous generations, indicating a scaling path that is already tangible.
High reliability manufacturers and suppliers highlight that the combination of low consumption, practically infinite resistance, high performance and scalability make this MRAM an optimal alternative in defense, aerospace, automotive and critical embedded systems, where non-volatility adds an extra layer of security against blackouts or failures.
Essential Comparisons: MRAM vs. SRAM, DRAM, and Flash
MRAM combines the virtues of several technologies: It is not volatile like flash, accelerates reads and writes almost to the level of SRAM and offers densities closer to DRAM. Compared to DRAM, it avoids refreshes (which occur around thousands of times per second in DRAM), reducing idle power consumption and control complexity.
In terms of speed, accesses have been documented in the order of 2 ns in MRAM laboratory, outperforming DRAM with more modern processes. Compared to flash, the difference in write speed is huge: there's no need for 10 V pulses with slow charge pumps or cycle degradation, so the lifespan is much longer.
Typical values: to take a picture of the memory map today:
| Comparative | MRAM | SRAM | DRAM | Flash |
|---|---|---|---|---|
| Volatility | No | Yes | Yes | No |
| Speed | High | Very high | High | Low in writing |
| Consumption | Low | High | Medium | Very low at rest |
Nota: MRAM stands out for its wear resistance, sustaining millions/billions of write cycles without appreciable degradation, something beyond the reach of conventional flash.
STT-MRAM vs. Other Non-Volatile RAMs: The Numbers That Matter
Within the MRAM family, the STT-MRAM It presents measurable advantages over non-volatile alternatives such as FORWARD, NVSRAM, or Toggle MRAM. Typical timing, cycle times, and retention ranges are as follows:
| Stitch | STT-MRAM | FORWARD | NVSRAM | Toggle MRAM |
|---|---|---|---|---|
| Type | Not volatile | Not volatile | Not volatile | Not volatile |
| Writing Instruments | Overwrite | Overwrite | Overwrite | Overwrite |
| Write latency | ~25 ns | ~150 ns | ~25 ns | ~35 ns |
| R/W Cycles | ~1e13 | ~1e14 | ~1e7 | ~1e13 |
| Retention | > 20 years | ~10 years | ~20 years | > 20 years |
Compared to EEPROM, Flash, SRAM and FRAM, STT-MRAM offers overwrite writing and without charge pumps, with a much higher durability than EEPROM/flash, and without the need for a battery like certain SRAMs with backup:
| Stitch | STT-MRAM | EEPROM | Flash | SRAM | FORWARD |
|---|---|---|---|---|---|
| Type | Not volatile | Not volatile | Not volatile | Volatile | Not volatile |
| Writing method | Overwrite | Delete+Write | Delete+Write | Overwrite | Overwrite |
| Typical writing | ~25 ns | ~10 μs | ~10 μs | ~5 ns | ~150 ns |
| R/W Cycles | ~1e13 | ~1e6 | ~1e5 | Unlimited | ~1e14 |
| charge pump | No | Yes | Yes | No | No |
| back-up battery | No | No | No | In some | No |
Technical challenges: scaling, currents and half-select
Not everything is perfect. The manufacturing of MRAM cells requires precise nanometric processes and complex stacks. In classic designs, the current required for writing was high, and the half-select phenomenon (interference between neighboring cells) limited miniaturization to nodes around 180 nm; variants with "toggling" pushed it to ~90 nm.
To compete on cost per bit with DRAM/flash, MRAM must move to smaller nodes (historically, the 65 nm bar set a target), and that has motivated the jump to STT first and, now, to SOT with heavy layers like tungsten. SOT-MRAM helps reduce current, separate R/W paths and gain speed, three pieces of the same puzzle.
The economic factor also weighs in: cost per bit and the useful density when packing large arrays. Still, the arrival of commercial STT products and the maturity of 300 mm processes are signs that the ecosystem is moving in the right direction.
The immediate goal is to lower the power per bit without sacrificing thermal stability margin or TMR, and to do so in a standard CMOS flow Compatible with the metal back-end of the leading nodes. The tungsten layer and its high torque efficiency are a natural ally in this endeavor.
Timeline and market maturation
The story goes back a long way. From the ferrite core memory In the 50s, through the discovery of magnetoresistors in thin films (IBM, 1989) and the wave of collaborations (IBM-Infineon, 2000; NVE with Cypress, 2002), MRAM has been climbing milestones with prototypes of 128 KiB and 1–16 Mibit in 180–150 nm processes in the mid-2000s.
In 2004–2006 we saw TSMC, NEC, Toshiba and Renesas show faster prototypes (up to 200 Mbit/s with 34 ns cycles and 1,8 V), record-breaking cell speeds at 2 GHz, and the emergence of MgO barriers that improved write performance. Although some companies withdrew, the field remained alive, with Freescale marketing 4 Mbit chips at the time.
The irruption of STT-MRAM changed the rules: Sony showed off the first SOT-MRAM lab prototype in 2005; and in 2018, Intel announced volume production of MRAM, making it clear that the technology was no longer just a promise. Since then, the focus has been on bringing SOT-MRAM to mass production as a real alternative to certain SRAMs.
In terms of uses, the range is enormous: military and aerospace, smart cards, mobile phones, cameras, PCs, base stations, SRAM replacement with battery and special memories for "black box" recorders. The vision of "universal memory"—a single technology to cover multiple roles—is not far-fetched.
New routes: multiferroics and electric field for writing
In addition to SOT, there are disruptive fronts that look to the magnetization by electric fieldResearchers have presented heterogeneous multiferroic structures with thin layers—for example, integrating vanadium between ferroelectric and piezoelectric materials—that stabilize magnetization directions and allow them to be reversed by applying electric current, further reducing switching energy.
These proposals demonstrate investment in the stable magnetic steering without continuous power supply and aim for even longer-lasting and energy-efficient MRAMs. Issues remain to be resolved, such as the degradation of switching efficiency over time, but the potential for high-performance, low-power computing is clear.
In parallel, other works have shown that incorporating a nanometric platinum film beneath the magnetic layers improves switching dynamics, supporting the idea that fine engineering of interfaces and heavy materials (W, Ta, Pt) is one of the clearest accelerators towards next-generation commercial SOT products.
Key Applications: From SRAM to AI, IoT and Cloud
Can SOT-MRAM replace SRAM? In raw performance, SRAM still rules; but SOT-MRAM makes up for it with no volatility, lower energy and reasonable scalability. For large caches, high-speed NVM, or near-memory computing, the balance starts to favor SOT at certain levels of the hierarchy.
In the automotive industry, MRAM is already demonstrating advantages: very fast reading, ultra-low power consumption and high density compared to eFlash/eSRAM, driving the transition to smarter vehicles. In mobile phones and wearables, it simplifies designs by consolidating memory subsystems, reducing power consumption and extending battery life without sacrificing performance.
In PCs and embedded systems, MRAM can act as non-volatile cache, replace NOR/SRAM in firmware and, over time, even come close to covering scenarios traditionally reserved for DRAM or PSRAM when absolute latency is not the number one limiting factor.
For data centers and AI, the promise of a technology that does not consume energy at restWith ultra-fast writes and extreme endurance, this translates into a lower TCO and a reduced carbon footprint. Add in the ability to operate without an auxiliary field, and the operating equation becomes very attractive.
Looking at the array of advancements—field-free tilted cells, tungsten/platinum layers for efficient SOT, and multiferroic approaches—MRAM is gaining ground as a cornerstone of high-performance, low-power electronics. The next step is to consolidate these pieces in production nodes with competitive yields.
The current photograph is of a technology that, from commercial STT variants in aerospace and embedded to record-breaking SOT prototypes, fits perfectly with the AI and IoT roadmap. If cost per bit and scaling hold, we'll see tungsten-layer SOT-MRAM and related technologies integrated ever closer to computing, even within general-purpose SoCs.
Everything points to the combination of speed (0,35 ns), tiny writing energy (156 fJ), high thermal stability (E/kBT~70) and high TMR (~170%) will make its mass adoption viable, as long as the fab ecosystem supports it with 300 mm processes and impeccable CMOS compatibility.
Without uncorking the champagne before its time, the path is laid outSTT-MRAM already solves real problems in critical markets; SOT-MRAM, supported by tungsten layers and other material engineering, provides the necessary refinement to compete with SRAM in certain memory layers; and multiferroic vias offer an extra trump card to further reduce power per bit. Magnetoresistive memory is consolidating as a serious candidate to be the wild card modern computing needed.
